參數(shù)資料
型號: LC72130
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24
封裝: SDIP-24
文件頁數(shù): 9/22頁
文件大?。?/td> 306K
代理商: LC72130
2. IF Counter Operation
Prior to starting the IF counter, reset the IF counter in advance by setting CTE in the serial data to zero.
The IF counter is started by changing the value of CTE in the serial data from zero to one. The serial data is latched
when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between
the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at the end of
the measurement period must be read out during the period that CTE is 1. This is because the IF counter is reset
when CTE is set to 0.
Note: When operating the IF counter, the control microprocessor must check for the presence of the IF-IC SD
(station detect signal) and, must turn on the IF buffer output and operate the counter only if the SD signal is
present. Autosearch techniques that use only the IF counter are not recommended, since it is possible for IF
buffer leakage output to cause incorrect stops at points where there is no station.
IFIN minimum input sensitivity standard
f (MHz)
( ): Actual values (reference data)
No. 4973-17/22
LC72130, 72130M
IFS
0.4
≤ f < 0.5
0.5
≤ f < 8
8
≤ f ≤ 12
1: Normal mode
40 mVrms
(0.1 to 3 mVrms)
(1 to 10 mVrms)
0: Degradation mode
70 mVrms
(10 to 15 mVrms)
(30 to 40 mVrms)
相關(guān)PDF資料
PDF描述
LC7218 PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24
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