參數(shù)資料
型號(hào): LC72131KM
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: 0.300 INCH, MFP-20
文件頁(yè)數(shù): 21/22頁(yè)
文件大?。?/td> 200K
代理商: LC72131KM
LC72131K, 72131KM
No.A0788-8/22
Continued from preceding page.
Pin No.
Symbol
LC72131K
LC72131KM
Type
Functions
Circuit configuration
PD
18
16
Charge pump
output
PLL charge pump output
When the frequency generated by dividing the local oscillator
frequency by N is higher than the reference frequency, a high
level is output from the PD pin.
Similarly, when that frequency is lower, a low level is output.
The PD pin goes to the high impedance state when the
frequencies match.
AIN
AOUT
19
20
17
18
LPF amplifier
transistors
The n-channel MOS transistor used for the PLL active
low-pass filter.
IFIN
12
11
IF counter
Accepts an input in the frequency range 0.4 to 12MHz.
The input signal is directly transmitted to the IF counter.
The result is output starting the MSB of the IF counter using the
DO pin.
Four measurement periods are supported: 4, 8, 32, and 64ms.
DI Control Data (Serial Data Input) Structure
[1] IN1 mode
[2] IN2 mode
R2
R1
R0
(3)
IF
-C
TR
XS
CTE
DVS
SNS
P15
P14
P13
P12
P11
P10
(1)
P-
CTR
(2)
R
-CT
R
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
R3
address
0
1
0
1
0
DI
0
First Data IN1
TEST1
TEST0
IFS
(12)
TEST
(11)
I
F
S
(10)
PD
-C
(5)
O-P
O
RT
(13)
D
on’t
care
(6)
D
O
-C
(9)
TI
ME
DLC
TBC
GT1
GT0
DZ1
DZ0
UL1
UL0
DOC2
DOC1
(7)
U
N
LO
CK
(4)
I
O
-C
(8)
D
Z
-C
(3)
IF
-C
TR
DOC0
DNC
BO
4
BO
3
BO
2
BO
1
IO2
IO1
IOC2
IOC1
TEST2
address
0
1
0
1
0
DI
1
First Data IN2
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