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參數資料
| 型號： | LC72136 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning(用于電子調諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調諧（用于電子調諧的鎖相環(huán)頻率合成器） |
| 文件頁數： | 12/23頁 |
| 文件大?。?/td> | 369K |
| 代理商： | LC72136 |
Continued from preceding page.
DO Output Data (Serial Data Output) Structure
3. OUT mode
DO Output Data
No. 5038-12/23
LC72136, 72136M
No.
Control block/data
Description
Related data
IF counter control data
IFS
This data should be set to 1 in normal operation. Setting this data to 0 switches
the LC72136 to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
*
See the “IF Counter Operation” item for details.
(11)
LSI test data
TEST 0 to 3
LSI test data
TEST0
TEST1
TEST2
(12)
All three bits must be set to 0.
All the test data is set to 0 following a power-on reset.
No.
Control block/data
Description
Related data
I/O port data
I2, I1
Data latched from the states of the I/O ports, pins IO1 and IO2.
(This data reflects the pin states, regardless of whether they are in input or output mode.)
I1
←
IO1 pin state
High: 1
I2
←
IO2 pin state
Low: 0
Data latched from the state of the unlock detection circuit
UL
←
0: Unlocked
UL
←
1: Locked or in detection stopped mode
Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19
←
Binary counter MSB
C0
←
Binary counter LSB
PLL unlock data
UL
IF counter binary data
C19 to C0
(1)
(2)
(3)
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
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| LC72136M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
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