- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄43903 > LC72140 PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 PDF資料下載
參數(shù)資料
| 型號： | LC72140 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 |
| 封裝： | DIP-24 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 321K |
| 代理商： | LC72140 |
LC72140, 72140M
No.4464–12/15
Table 15. Input sensitivity
S
V
DS
N
St
u
p
n
I)
z
H
M
(
y
c
n
e
u
q
e
r
F)
V
m
(
y
t
i
v
i
t
i
s
n
e
s
m
r
t
u
p
n
I
1
×
N
I
M
F
0
1 ≤
0
5
<
f0
0
1
0
5 ≤
0
3
1
<
f0
7
0
3
1
≤
0
6
1
<
f0
0
1
01
N
I
M
A
2 ≤
5
2
<
f0
4
5
2 ≤
0
4
<
f0
7
00
N
I
M
A
5
.
0
≤
5
.
2
<
f0
4
5
.
2
≤
0
1
<
f0
7
Note
×=don’t care
General-purpose Counter
The 20-bit general-purpose counter is used for both frequency and period measurement as shown in Figure 10. The
measurement mode is selected by bits CTS0 and CTS1. The counter contents, C, in frequency measurement mode are
given by
C=FIF
× GT
and in period measurement mode by
C=
÷ 900kHz
The counter contents are output on DO, msb first.
The LCTR signal is passed directly to the counter input. The HCTR signal is passed through a divide-by-two prescaler.
The actual HCTR frequency is, therefore, two times the measured frequency. The timing for the general-purpose counter
is shown in Figure 11.
Figure 10. General-purpose counter
Figure 11. General-purpose counter timing
Note
tWU=wait time
The counter starts when the CTE flag is set. The serial input data is latched in on the falling edge of CE. Note that the
HCTR or LCTR input signal should be input within the wait time of this transition.
The period or frequency count should be read while CTE is set to 1, because the counter is reset when CTE is set to 0.
Note that CTE should be set to 0 before each measurement.
In IF count mode, the IF IC’s SD (station detector) signal presence is determined by the microcontroller and if an SD
signal is present, the IF count buffer output turns ON and IF count becomes active. During auto-search in IF count only,
there is a possibility of the count stopping even when there is no station present due to the IF count buffer output leakage.
1
T
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC72146 | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24 |
| LC72146V | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| LC72146M | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| LC72147V | PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24 |
| LC72148V | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72140M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
| LC72144M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72146 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72146M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72146MA-AH | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。