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參數(shù)資料
| 型號(hào)： | LC72191M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大小： | 318K |
| 代理商： | LC72191M |
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DO Output Format (serial data output)
The LC72191 includes a 28-bit internal shift register that can be used to output the following data from DO: the IN0 and
IN1 input port states, the general-purpose counter (20-bit binary counter) and the unlock detection circuit state.
The contents of the shift register is latched at the point that serial data output mode is selected.
No. 3985-9/16
LC72191, 72191M, 72191JM
No.
Control block/data
Description
Related data
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Divider selection data
DV
Sensitivity selection
data
SP
General-purpose
counter input pin
selection data
SC
General-purpose
counter
frequency/period mode
switching data
SF
General-purpose
counter count time
selection data
GT
Time base output
control data
TB
LSI test mode control
data
T0, T1
DV selects the local oscillator input pin. (FMIN or AMIN)
SP switches the input frequency range when AMIN is selected.
* don’t care
SC selects the input pin (HCTR or LCTR) for the general-purpose counter.
SF selects the measurement type (frequency or period) when LCTR is selected.
When HCTR is selected, SF is ignored and the LC72191 operates in frequency measurement
mode.
* don’t care
GT selects the measurement time in frequency measurement mode and the number of periods
in period measurement mode.
GT = 0: 12 ms/one period
GT = 1: 24 ms/two periods
(frequency measurement/period measurement)
When TB is set to 1 an 8 Hz 40% duty clock time base signal is output from OUT0. O0 bit is
ignored in this mode.
T0 and T1 switch the LSI between test and normal operating modes. The test modes and have
no user related functions. Both T0 and T1 must always be set to 0.
Be sure to set both T0 and T1 to 0 after power is applied.
CTEN
GT
CTEN
SC
SF
O0
DV
SP
Input pin
Input frequency range (MHz)
1
*
FMIN
10 to 130
01
AMIN
2 to 40
00
AMIN
0.5 to 10
DV
SP
Input pin
Measurement type
1
*
HCTR
Frequency measurement (sine wave)
01
LCTR
Frequency measurement (sine wave)
00
LCTR
Period measurement (pulse waveform)
No.
Data
Description
(1)
Input port data
The values of the IN0 and IN1 input ports are latched into I0 and I1.
I0 and I1
I0 ← IN0, I1 ← IN1
General-purpose
The C19 to C0 data is latched from value of the general-purpose 20-bit binary counter.
(2)
counter binary data
C19 ← 20-bit binary counter MSB
C19 to C0
C0 → 20-bit binary counter LSB
The UL3 to UL0 data is latched from the unlock detection circuit.
PLL unlock state data
UL0: 1.11
(3)
UL3 to UL0
UL1: 2.22
These bits are set to 1 if a phase difference in excess of these times (in s) was detected.
UL2: 3.33
(for a 7.2 MHz crystal)
UL3: 0.55
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