參數(shù)資料
型號(hào)： LC72713W
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁(yè)數(shù)： 20/29頁(yè)
文件大小： 158K
代理商： LC72713W
LC72713W
No.6870-27/29
Figure 7 shows the flow of the dGPS data reception sequence focusing on the block synchronization state. Block
synchronization is immediately set to the unsynchronized state by BLK_RST, and the IC then reacquires block
synchronization with the dGPS station. Of course, if the dGPS station reception conditions are unfavorable, time will
pass without acquiring block synchronization. In the example shown in this figure, the period during which VICS
station data cannot be acquired with horizontal correction processing is a 6-packet period. Since the ability of vertical
correction to correct burst errors is about 10 packets, this example has a margin of about 4 packets. This margin can be
applied to the period for establishing block synchronization with the dGPS station. That is, the best timing for tuning
from the VICS station to the dGPS station is about 4 packet positions before the position of the packet that has dGPS
data.
Notes
(1) The approach of using a single tuner for channel selection in the acquisition of both VICS and dGPS data, has
certain disadvantages from the standpoint of complete acquisition of the VICS data. This is because the VICS
station data transmitted while the tuner is tuned to the dGPS station will be handled as invalid data or bad packet
data. While the inherent vertical error correction capability is 10 to 12 bits, if we subtract the number of incorrect
VICS station packets during dGPS station reception, it is clear that this will seriously reduce the reliability of
recovery based on vertical error correction of the VICS data. This point must be taken into consideration.
(2) When using the control technique described above, the time allowed for dGPS data acquisition will be the time
required for about 10 packets. We recommend using the following synchronization system settings in order to
acquire the dGPS packet data within such a brief time. The reason the number of allowable BIC errors is
changedto a more strict value is to reduce the occasions where incorrect BICs are checked. However, even with
these settings, it may not be possible to lock synchronization with the set protection count if the reception
conditions are poor.
Default setting
Recommended setting
Number of allowed BIC errors (backward)
2
1
Block synchronization error protection count (backward)
1
1 (The default value can be used)
Frame synchronization error protection count (forward)
7
3 or higher (The default value can be used)
(3) Bit 7 in control register 2 (SUB BLK) must be set to 1 during dGPS data reception. If this flag is not set, decoding
for the VICS data vertical correction may not complete.
Missing
data 1
Missing
data 2
Missing
data 3
Missing
data 4
Missing
data 5
Missing
data 6
OK dGPS
data
OK dGPS
data
OK
data
Bad
data
Bad
data
Bad
data
OK
VICS data
Tuning tke dGPS station
BLK RST
VICS station
block period
dGPS station
block period
IC block
synchronization
Post-horizontal
correction output
INT signal
dGPS data
Tuning tke VICS station
BLK RST
Figure 7 VICS-dGPS Simultaneous Reception
Protection
count: 2
Protection
count: 1
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