參數(shù)資料
型號(hào)： LC72714W
廠商： SANYO SEMICONDUCTOR CO LTD
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁(yè)數(shù)： 17/29頁(yè)
文件大?。?/td> 201K
代理商： LC72714W
LC72714W
No.6871-24/29
Notes on Simultaneous Reception of VICS and dGPS Data
Currently, VICS service data and dGPS service data are broadcast from different stations. Since the amount of the dGPS
data is small, 2 packets per frame, it is possible to receive both VICS data and dGPS data with a single tuner by
controlling the tuning of the receiver during the reception of mainly VICS data. During this operation, only the results
of horizontal error correction are used for dGPS data, and the VICS data that is missing due to the reception of dGPS
data is decoded (recovered) by using vertical direction error correction. (Caution: If there are any bad packets other than
the missing data, it may not be possible to recover the data.)
This IC includes functions that allow simultaneous acquisition of both VICS and dGPS data by controlling the tuning of
a single tuner. The following section describes the procedure for data reception using this function.
Notes on block and frame synchronization
circuit operation
Normally, if the block synchronization system
issues an incorrect synchronization, the count
timing of the frame synchronization counter,
which is based on the block synchronization,
changes along with that error. If this state
continues for an extended period, the frame
synchronization circuit will take this new block
synchronization timing to be correct, and discard
the timing based on the original station A. This is
the situation that occurs during normal tuning.
That is, after the time for the frame synchronization
forward protection count has passed, frame
synchronization is lost, and then after the time
for the frame synchronization back protection
count has passed,
synchronization is established with a synchronization
timing that is different from that of station A,
which had been the prior situation. Also, even if
there is a block synchronization error for a short
period, the temporary change in the block period
can cause a timing discrepancy in the frame
synchronization counter, which is based on the
block synchronization.
This IC includes a compensation function to handle temporary incorrect synchronization in the block synchronization
circuit. What we are referring to as temporary incorrect synchronization in the block synchronization circuit is the
phenomenon shown in figure 6. Here, while the system is mainly receiving station A, the signal-to-noise ratio is
degraded for some reason and the circuit synchronizes with a timing that does not actually exist. After that, the circuit
resynchronizes with the block synchronization timing for the original station A due to, for example, improved reception
conditions. Even if such a condition occurs, the functions included in this IC allow it to actually acquire all the data that
can be acquired and furthermore, the synchronization circuit will not disrupt those conditions.
dGPS data
VICS data
Tuning
One frame
Frame phase
difference
Missing data
Figure 5 VICS and dGPS Data
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