參數(shù)資料
型號: LC72720M
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip RDS Signal-Processing System LSI
中文描述: 單芯片發(fā)展策略的信號處理系統(tǒng)LSI
文件頁數(shù): 10/14頁
文件大?。?/td> 235K
代理商: LC72720M
No. 5602-10/14
LC72720, 72720M
Caution: The output indicates the synchronization state for the previous block.
Mode (PT2 = 0)
The SYNC pin
0 to 2
When synchronized: Low (0). When unsynchronized: High (1)
When synchronized: Goes high for a fixed period (421 μs) at
the start of a block and then goes low.
When unsynchronized: High (1)
3
When PT2 = 0
The RDS-ID pin
No RDS
High (1)
RDS present
Low (0)
10. Test mode settings (4 bits): TS0 to TS3
Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above values.)
Notes: The T1 and T2 pins (pins 7 and 8) are related to test mode as follows:
The T1 pin must be tied to V
SS
(0 V).
Initial values: CT0 = 0, CT1 = 0
Pin T1
Pin T2
LSI operation
Notes
0
0
Normal operating mode
These states are user settable
0
1
Standby mode (crystal oscillator stopped)
1
0/1
LSI test mode
Users cannot use this state
11. Circuit control (2 bits): CT0 and CT1
RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing
Timing 1 (modes 1 to 3, PT2 = 0)
Timing 2 (mode 3, PT2 = 0)
Item
Control
CT0
RSFT control
When set to 1, soft-decision control data (RSFT) is easier to generate.
CT1
RDS-ID detection condition
When set to 1, the RDS-ID detection conditions are made more restrictive.
RDCL output
RDDA output
RSFT output
Input data
Error crrection
SYNC output
ERROR output
CORREC output
Sync NG
Sync NG
Sync NG
Sync OK
Sync OK
Sync OK
Sync OK
Sync OK
Data
corrected
Data
corrected
No
errors
No
errors
U
U
Note: When PT2 = 0, RDDA and RSFT must be
aquired on the falling edge of RDCL.
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