
LC7441N, 7441NE
No.3941–13/20
Register data can be written when the controller is in
standby mode, but memory data is lost because the PLLs
are stopped and the memory is not refreshed.
Dual-port RAM Interface
The dual-port RAM interface comprises the SODI0 to
SODI3 inputs and A0 to A7, WDO0 to WDO3, WE, DT,
RAS, CAS and SC outputs.
The LC7441 and the dual-port RAM should be mounted
as closely as possible and care taken with the PCB
layuout because of the high speed of memory accesses.
The data read, memory refresh and data transfer wave-
forms are shown in figures 1, 2 and 3, respectively. Note
that when RAR is HIGH, t = 1/1696fH if NTSC/PAL is
also HIGH, and t = 1248fH if NTSC/PAL is LOW.
Reset and Standby Modes
The controller is reset by holding RES LOW and put in
standby mode by either holding SBY LOW or setting the
SBY register HIGH. The PLLs are stopped and the
internal registers set as shown in the following table.
Note that the input levels are used to determine some
initial register values. For example, if KDIS is LOW
when RES is brought LOW, then the KOUT, KOUT1 and
KOUT2 registers are set LOW.
Note
– Register unchanged
At power-up, hold RES LOW for several microseconds
after the power supply stabilizes as shown in the follow-
ing figure. Note that S and E represent the start and the
end of PIP controller operation, respectively.
r
e
t
s
i
g
e
Rt
e
s
e
Ry
b
d
n
a
t
S
Y
B
SW
O
L–
,
1
R
A
V
K
W
,
R
A
V
K
W
2
R
A
V
K
W
O
L–
D
L
I
FW
O
L–
,
1
T
U
O
K
,
T
U
O
K
2
T
U
O
K
S
I
D
KS
I
D
K
R
A
V
S
O
PW
O
L–
2
L
T
S
,
1
L
T
S
,
L
T
SL
T
S
/
E
D
SL
T
S
/
E
D
S
R
P
V
FP
V
F
/
K
C
SP
V
F
/
K
C
S
R
P
H
FP
H
F
/
D
SP
H
F
/
D
S
I
R
PH
G
I
H–
r
e
t
s
i
g
e
Rt
e
s
e
Ry
b
d
n
a
t
S
E
P
I
W
VW
O
L–
E
P
I
W
HW
O
L–
5
P
V
o
t
0
P
V–
–
5
P
H
o
t
0
P
H–
–
2
K
W
,
1
K
WK
W–
1
S
F
D
VW
O
L–
0
S
F
D
VH
G
I
H–
5
K
W
Y
o
t
0
K
W
Y–
–
5
K
W
R
o
t
0
K
W
R–
–
5
K
W
B
o
t
0
K
W
B–
–
R
A
R
,
L
U
MW
O
L–