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參數(shù)資料
| 型號(hào)： | LC74751 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display LSI |
| 中文描述： | 屏幕顯示大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 439K |
| 代理商： | LC74751 |
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Memory Organization (display RAM and control RAM)
Both memory addresses and data are 16-bit quantities.
The locations at addresses 000 (000 hexadecimal) to 175 (0AF hexadecimal) hold display memory (RAM) data.
The locations at addresses 176 (0B0 hexadecimal) to 191 (0BF hexadecimal) hold display control register data.
No. 5396-6/15
LC74751
Bit
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
Notes
Address
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
000
(000h)
0
0
0
0
0
0
0
0
ATTR
C6
C5
C4
C3
C2
C1
C0
ATTR
Character code
Display RAM
175
(0AFh)
0
0
0
0
0
0
0
0
ATTR
C6
C5
C4
C3
C2
C1
C0
176
(0B0h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the first line
177
(0B1h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the second line
178
(0B2h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the third line
179
(0B3h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the fourth line
180
(0B4h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the fifth line
181
(0B5h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the sixth line
182
(0B6h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the seventh line
183
(0B7h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the eighth line
184
(0B8h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the ninth line
185
(0B9h)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the tenth line
186
(0BAh)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the eleventh line
187
(0BBh)
0
0
0
0
0
ADR
A
ADR
9
ADR
8
ADR
7
ADR
6
ADR
5
ADR
4
ADR
3
ADR
2
ADR
1
ADR
0
Display line ROM specification
First character in the twelfth line
188
(0BCh)
0
0
0
0
HSZ
31
HSZ
30
HSZ
21
HSZ
20
HSZ
11
HSZ
10
HP5
HP4
HP3
HP2
HP1
HP0
Horizontal display position
Horizontal character size
189
(0BDh)
0
0
0
0
VSZ
31
VSZ
30
VSZ
21
VSZ
20
VSZ
11
VSZ
10
VP5
VP4
VP3
VP2
VP1
VP0
Vertical display position
Vertical character size
190
(0BEh)
0
0
0
0
INT/
NON
LC/
XTAL
2fsc/
4fsc
OSC
STP
DSP
ON
MUTE
SYS
RST
SIG
MD1
SIG
MD0
PHASE PHASE PHASE
2
1
Video signal and other items
0
191
(0BFh)
0
0
0
0
TST
MOD
VSN
SEP
0
BLK
1
BLK
0
RVS
ON
BLINK BLINK BLINK
2
1
EXT/
INT
CBOFF BCOL
Control register
0
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