參數(shù)資料
型號： LC74776
廠商： Sanyo Electric Co.,Ltd.
英文描述： On-Screen Display Controller IC
中文描述： 屏幕顯示控制器IC
文件頁數(shù)： 3/35頁
文件大?。?/td> 253K
代理商： LC74776
Pin Functions
No. 6018-3/35
LC74776, 74776M
Pin no.
Pin
Function
Notes
1
V
SS
1
Ground
Ground connection (digital system ground)
2
Xtal
IN
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to function as
the MUTE input pin. When this pin is set low, the video output is held at the pedestal level.
(A pull-up resistor is built in and the input has hysteresis characteristics.)
Xtal
OUT
(MUTE)
Crystal oscillator
(MUTE input)
3
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character
.
frame)
output. This is a 3-value output.
4
CTRL1
(CHABLK)
5
SCL
I
2
C clock input
Clock input for the PDC/VPS data output. I
2
C bus.
6
OSC
IN
LC oscillator
connections
Connection for the external coil and capacitor for the oscillator used to generate
the character output dot clock
7
OSC
OUT
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs
a high level when synchronizing signals are present.
Outputs either the crystal oscillator clock if CS and RST are low, or the VCO clock if CS
and RST are high.
(This signal is not output after a command reset.)
External synchronizing
signal judgment output
8
SYNC
JDC
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
9
CS
Enable input
10
SCLK
Clock input
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN
Data input
Serial data input.
A pull-up resistor is built in and the input has hysteresis characteristics.
12
V
DD
2
CP
OUT
VCO
IN
V
SS
3
VCO
R
NC
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
14
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
15
Ground
Ground (VCO ground)
16
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
17
This pin must either be connected to ground or left open
18
V
DD
3
CV
OUT
V
SS
2
CV
IN
CV
CR
V
DD
1
SYN
IN
SEPC
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
19
Video signal output
Composite video signal output
20
Ground
Ground (analog system ground)
21
Video signal input
Composite video signal input
22
Video signal input
SECAM chrominance signal input
23
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
Sync separator circuit input
Video signal input to the internal sync separator circuit
25
Slice level output
Slice level verification pin
26
SEP
OUT
Composite synchronizing
signal output
Internal sync separator circuit composite synchronizing signal output. The signal actually
output can be switched by MOD0 and SEL0. The DAV signal is output in the initial state.
PDC/VPS data I/O.
The I
2
C bus write address is [0111 1100].
The I
2
C bus read address is [0111 1101].
27
SDA
I
2
C bus data I/O
28
CDLR
Background color phase
adjustment
Background color phase adjustment resistor connection
29
RST
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
30
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Note:
*
Both V
DD
1 pins must be connected to power.
Crystal oscillator input
switching
(CHABLK)
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