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參數(shù)資料
| 型號： | LC74789M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | 0.375 INCH, PLASTIC, MFP-24 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 209K |
| 代理商： | LC74789M |
No. 5732-16/23
LC74789, 74789M, 74789JM
COMMAND7 (Display control setup command)
First byte
DA
Register
Contents
Notes
0 to 7
State
Function
7
—
1
6
—
1
Command 7 identification code.
5
—
1
Display control setup.
4
—
1
3
—
0
Extended command 0 identification code
2
—
0
1
SEL1
0
Vertical synchronizing signal (external V separation) input
Switches the SEPIN (pin 20) input.
1
Frame signal input
Only valid when CTL3 is high.
0
CTL3
0
Use internal V separation
Switches V separation.
1
Do not use internal V separation
Second byte
DA
Register
Contents
Notes
0 to 7
State
Function
7
—
0
Second byte identification bit
6
CINSEL
0
Blanking area (The logical OR of the character and frame signals)
CVCR on signal switching
1
Video signal display area
5
CINCTL
0
CVCR: off
CVCR on/off setting
1
CVCR: on
4
VNPSEL
0
V falling edge detection
Switches the V acquisition polarity in external mode
1
V rising edge detection
when internal V separation is used.
3
VSPSEL
0
VSEP: about 8.9 s (for NTSC)
Switches the internal V separation period.
1
VSEP: about 17.8 s (for NTSC)
2
MSKERS
0
Mask valid
Clears the HSYNC and VSYNC masks.
1
Mask invalid
1
MSKSEL
0
3H (for NTSC)
Switches the VSYNC mask.
1
20H (for NTSC)
0
EGL
0
Frame level 0 only (VBK0)
Switches the frame level.
Note: All registers are set to 0 when the LC74786/M/JM is reset by the RST pin.
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