參數(shù)資料
型號(hào)： LC74793JM
廠商： Sanyo Electric Co.,Ltd.
英文描述： VPS / PDC Slicer IC
中文描述： 車輛定位系統(tǒng)/ PDC的切片機(jī)集成電路
文件頁(yè)數(shù)： 3/24頁(yè)
文件大?。?/td> 154K
代理商： LC74793JM
No. 5966-3/24
LC74793, 74793JM
Pin Functions
Pin No.
Pin
Function
Description
1
V
SS
1
Xtalin
Ground
Digital system ground
2
Crystal oscillator connections
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
3
Xtalout
4
CTRL1
Crystal element switching
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
5
NC
Data I/O
I
2
C bus
PDC/VPS data I/O.
I
2
C bus write address: 01111100
I
2
C bus read address: 01111101
6
SDA
7
SCL
Clock input
I
2
C bus
PDC/VPS data clock input.
I
2
C bus
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
8
SYNC
JDG
External synchronizing signal
discrimination output
9
Hout
Horizontal synchronizing signal output
Horizontal synchronizing signal output
10
VSS2
Ground
Ground. (VCO circuit ground)
11
CP
OUT
VCO
IN
VCOR
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
12
Oscillator control voltage input
VCO oscillation control voltage input
13
Oscillator range adjustment
VCO oscillation range adjustment resistor connection
14
DAV
Data acquisition output
Outputs a low level when PDC/VPS data has been discriminated
15
V
DD
2
SYNin
Power supply (+5 V)
Power supply (+5 V) (VCO system power supply)
16
Sync separator circuit input
Internal sync separator circuit video signal input
17
SEPC
Slice level output
Slice level verification
18
SEP
OUT
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output
Inputs the vertical synchronizing signal by integrating the SEP out pin output signal.
Applications must connect the SEP out pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
19
SEP
IN
Vertical synchronizing signal input
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
20
Vout
Vertical synchronizing signal output
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPin
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
21
CTRL2
SEPin input control
22
CDLR
Clock phase adjustment
Connection for the clock phase adjustment resistor.
23
RST
Reset input
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
24
V
DD
1
Power supply (+5 V)
Power supply. (+5 V: digital system power supply)
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