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參數(shù)資料
| 型號： | LC74798 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display Controller IC(屏幕顯示控制器芯片) |
| 中文描述： | 屏幕顯示控制器IC（屏幕顯示控制器芯片） |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 271K |
| 代理商： | LC74798 |
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No. 5833-3/32
LC74798, 74798M
Pin Descriptions
Pin No.
Pin name
Function
Notes
Ground
Ground connection (digital system ground)
1
V
SS
1
Crystal oscillator
(MUTE input)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an
external clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to
function as the MUTE input pin. When this pin is set low, the video output is held at the
pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
Crystal oscillator input switching
(CHABLK output)
Switches the mode between external clock input and crystal oscillator operation. A low
level selects crystal oscillator operation and a high level selects external clock input. As a
mask option, the CTRL1 input pin can be set to function as the CHABLK (character ·
frame) output. This is a 3-value output.
2
Xtal
IN
3
Xtal
OUT
(MUTE)
4
CTRL1
(CHABLK)
Enable input 2
Enable input for the PDC/VPS data output. Data output is enabled when this input is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
5
CS2
Clock input 2
Clock input for the PDC/VPS data output.
A pull-up resistor is built in and the input has hysteresis characteristics.
6
SCLK2
Data output
PDC/VPS data output.
(This can be either an n-channel open-drain output or a CMOS output.)
7
DOUT
External synchronizing signal judgment
output
Outputs the state of the external synchronizing signal presence/absence judgment.
Outputs a high level when synchronizing signals are present.
Outputs the crystal oscillator clock when CS1 and RST are low.
(This signal is not output on command resets.)
8
SYNC
JDG
Enable input 1
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
9
CS1
Clock input 1
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
10
SCLK1
Data input 1
Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN1
Power supply
Composite video signal level adjustment power supply (analog system power supply)
12
V
DD
2
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
13
CP
OUT
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
14
VCOIN
Ground
Ground (VCO ground)
15
V
SS
3
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
16
VCO
R
Oscillator control voltage input 2
VCO oscillator control voltage input. For character display.
17
VCO
IN
2
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
18
V
DD
3
Video signal output
Composite video signal output
19
CV
OUT
Ground
Ground (analog system ground)
20
V
SS
2
Video signal input
Composite video signal input
21
CV
IN
Video signal input
SECAM chrominance signal input
22
CV
CR
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
23
V
DD
1
Sync separator circuit input
Video signal input to the internal sync separator circuit
24
SYN
IN
Sync separator circuit adjustment
Internal sync separator circuit adjustment
25
SEPC
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is
high.
26
SEP
OUT
Vertical synchronizing signal input
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output
signal.
An integration circuit must be connected between this pin and the SEP
OUT
pin. This pin
must be tied to V
DD
1 if unused. This pin is valid when CTL3 is set high.
27
SEP
IN
Background color phase adjustment
Background color phase adjustment resistor connection
28
CDLR
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
29
RST
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
30
V
DD
1
Note
*
: A capacitor of at least 2000 pF must be connected between the V
DD
1 power supply and V
SS
1.
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