參數(shù)資料
型號(hào): LC749880T
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP120
封裝: 14 X 14 MM, TQFP-120
文件頁(yè)數(shù): 12/17頁(yè)
文件大?。?/td> 112K
代理商: LC749880T
LC749880T
No.A1186-4/17
Continued from preceding page.
Signal type
No. of pins
Pin symbol
Description
Remarks
1
XIN
Clock
Crystal oscillator input pin (27MHz)
Clock
(1)
(DCLKO3)
Clock
(GPIO pin)
Clock input when MODE
≠0, 1
System reset
1
RESET
System reset
System reset input pin (Lo-Active)
I/F mode selection
3
MODE
I/F mode selection
I/F mode selection signal input pin
0: Two-phase 6-bit output (TCON signal output)
1: Single-phase 8-bit/6-bit output
(RGB, TCON signal output)
DCLKO3; 3.375MHz output
2: Single-phase 8-bit/6-bit output
(RGB, TCON signal output)
DCLKO3; Clock input
3,4: Decoder output (RGB/YCbCr/YC
(register setting), synchronizing signal output)
5: Single-phase 8-bit/6-bit output
(RGB, synchronizing signal output)
* Others not applicable because they are not defined.
2. Output Signals
Signal type
No. of pins
Pin symbol
Description
Remarks
(36)
(VP)
Digital I/F
(GPIO pin)
Video signal output pin. MODE pin. Pin function changed
through register setting. 6-bit output for output after dither
processing
For single-phase 8-bit output(MODE
≠0)
VP00 to VP07: R0 to R7(Cb0 to Cb7)
VP08 to VP15: B0 to B7(Cb0 to Cr7/CbCr0 to CbCr7)
VP16 to VP23: G0 to G7(Y0 to Y7)
* ( ) shows the YCbCr
4:4:4/4:2:2 output (MODE=3,4)
For single-phase 6-bit output (MODE
≠0)
VP00 to VP05: R0 to R5
VP08 to VP13: B0 to B5
VP16 to VP21: G0 to G5
For two-phase 6-bit output (MODE=0)
VP00 to VP05: RO0 to RO5
VP18 to VP23: RE0 to RE5
VP06 to VP11: BO0 to BO5
VP24 to VP29: BE0 to BE5
VP12 to VP17: GO0 to GO5
VP30 to VP35: GE0 to GE5
* xO: Odd-numbered picture elements
xE: Even-numbered picture elements
Video signal
1
SVO
Analog I/F
Internal analog video signal output
(1)
(TIM1)
Vertical synchronizing
(GPIO pin)
Applicable when MODE=3, 4, and 5. Synchronizing
period, Polarity reversal possible
Synchronizing
signal
(1)
(TIM2)
Horizontal synchronization
(GPIO pin)
Applicable when MODE
≠0. Synchronizing period.
Polarity reversal possible
Data enable
signal
(1)
(TIM0)
Data enable
(GPIO pin)
Applicable when MODE=3, 4, and 5. H,V composite
data enable output. Position, polarity reversal possible
Continued on next page
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