
LC749880T
No.A1186-5/17
Continued from preceding page.
Signal type
No. of pins
Pin symbol
Description
Remarks
(1)
(GRST)
When MODE=0, the gate reset signal output/clamp
pulse output/PWM3 output selectable through register selection
When MODE
≠0, the gate reset signal output/clamp
pulse output selectable through register selection
GRST: Pulse width, position, and polarity reversal possible
1
FLM
When MODE=0, 1, and 2, gate start pulse signal output
Pulse width, position, polarity reversal possible. Hi-Z
when FLM2 is used
1
OE
When MODE=0, 1, and 2, gate output enable signal output.
Pulse width, position, polarity reversal possible.
1
CPV
When MODE=0, 1, and 2, gate clock signal output.
Pulse width, position, polarity reversal possible.
1
STRB
When MODE=0, 1, and 2, source strobe signal output.
Pulse width, position, polarity reversal possible.
1
SP
When MODE=0, 1, and 2, source start pulse signal output.
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
1
DEXR
When MODE=0, 1, and 2, source picture element reversal signal
output.
When MODE=0, DEXR output of odd-numbered picture
elements
1
POL
When MODE=0, 1, and 2, source voltage polarity
selection signal output.
Position adjustment, 1 line/2 line reversal and 1 frame/2
frame reversal possible
(1)
(TIM0)
When MODE=0, 1, and 2, FLM2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when FLM is used
(1)
(TIM1)
When MODE=0,1, and 2, SP2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
TCON signal
(1)
(TIM2)
TCON signal
(GPIO pin)
When MODE=0, DEXR (DEXR_E) output of
even-numbered picture elements
1
DCLKO
Dot clock
Picture element clock output. Polarity reversal, 1/2
output possible
1
(DCLKO3)
When MODE=0 and 1, clock output (3.357MHz)
Clock
1
XOUT
Clock
Crystal oscillator output pin
1
VSO
Vertical synchronizing signal output for OSD (To
μ-CON)
Pulse width, position, polarity reversal possible.
1
HSO
Horizontal synchronizing signal output for OSD (To
μ-CON)
Pulse width, position, polarity reversal possible.
For OSD signal
1
DCLKO2
OSD I/F
Picture-element clock output for OSD (To
μ-CON)
Polarity reversal, 1/2 output possible
(1)
(VP32)
When MODE
≠0, PWM1 output through register setting.
Pulse width, position, polarity reversal possible.
(1)
(VP35)
When MODE
≠0, PWM2 output/PWM3 output/clamp pulse output
selectable through register setting.
PWM2, 3: Pulse width, position, polarity reversal possible.
PWM output
(1)
(GRST)
PWM signal
(GPIO pin)
When MODE=0, PWM3 output/GRST output/clamp pulse output
selectable through register setting
PWM3: Pulse width, position, polarity reversal possible.
(1)
(VP35)
When MODE
≠0, clamp pulse output/PWM2 output/PWM3 output
selectable through register setting
Clamp pulse: Pulse width and position adjustment possible.
Clamp pulse
(1)
(GRST)
Clamp pulse
(GPIO pin)
When MODE=0, clamp pulse output/GRST output/PWM3 output
selectable through register setting.
When MODE
≠0, clamp pulse output/GRST output selectable
through register setting
Clamp pulse: Pulse width and position adjustment possible.
* The signals in parentheses show that one pin has multiple functions or acts as the I/O pin.
Selection can be made with the MODE pin or through register setting.