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參數(shù)資料
| 型號： | LC78858V |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 16-BIT DAC, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 132K |
| 代理商： | LC78858V |
PS No. 5967-11/12
LC78858V
Power Supply Timing
The analog system power supplies (AVDDL and AVDDR) and the digital system power supply (DVDD) must be
applied and cut at the same time.
If time lags between these power supplies are unavoidable, the timing must meet one of the following two conditions.
(1) The power on (and power off) time lag must be under 3 ms as shown in figure 1.
(2) If the time lag must be over 3 ms, then the rise time for the first power supply to be powered on (or powered off)
must exceed 5 ms, and furthermore, the time difference must not exceed 50 ms as shown in figure 2.
Figure 1
Under 3 ms
Figure 2
Under 3 ms
Over 5 ms
Under
50 ms
Over
5 ms
Under
50 ms
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