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參數(shù)資料
| 型號(hào)： | LC80101M |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | MFP-28 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 161K |
| 代理商： | LC80101M |
No. 5438-2/9
LC80101M
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Clock low-level time
tCL
CL2
0.7
s
Clock high-level time
tCH
CL2
0.7
s
Data setup time
tSU
CL2, DI2
0.7
s
Data hold time
tHD
CL2, DI2
0.7
s
CE wait time
tEL
CL2, CE2
0.7
s
CE setup time
tES
CL2, CE2
0.7
s
CE hold time
tEH
CL2, CE2
0.7
s
Data output time
tDH
DO2: Varies with the value of the pull-up resistor used
1
s
Serial Input and Output (See the serial data timing figures.)
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
VIH
CMOS-compatible Schmitt inputs
0.8 VDD
V
Input low-level voltage
VIL
Pull-down resistors: INT-R1, TEST1 to TEST4,
0.2 VDD
V
and TESTON
Input high-level voltage
VIH
CMOS-compatible Schmitt inputs:
0.8 VDD
V
Input low-level voltage
VIL
BACKUP, CE2, CL2, DI1, DI2, and RST2
0.2 VDD
V
Output high-level voltage
VOH
IOH = –4 mA: CE1, CL1, DO1, INT-R2
VDD – 2.1
V
Output low-level voltage
VOL
IOL = 4 mA: CE1, CL1, DO1, INT-R2
0.4
V
Output low-level voltage
VOL
IOL = 2 mA: DO2
0.4
V
Standby current
Isd
With the BACKUP pin low
0.01
10
A
Input sensitivity
Vck
Rf = 1 M
, FILCK1 = 3.6 MHz: FILCK1*1
1.0
VDD
Vp-p
Pull-down resistance
Rd
INT-R1, TEST1 to 4, TESTON
70
140
280
k
IDD1
Sine wave input: 1 V p-p, VDD = 5.0 V*2
6
15
mA
Current drain
IDD2
Sine wave input: 5 V p-p, VDD = 5.0 V*2
2.5
7
mA
IDD3
Square wave input: 1 V p-p, VDD = 5.0 V*2
5
13
mA
IDD4
Square wave input: 5 V p-p, VDD = 5.0 V*2
1.5
4
mA
Electrical Characteristics/Input and Output Levels at Ta = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Note 1. Since this LSI operates based on the rising edge of the LC72700E 3.6 MHz output (the FILCK pin), the LC72700E 3.6 MHz output signal must be
input to the FILCK1 pin without inverting the polarity.
2. The current drain varies with the input level and the shape of the clock signal input to the FILCK1 pin. The current drain can be reduced by using
waveforms that are closer to square waves than to sine waves, and by using a signal level that is close to VDD. The LC72700E 3.6 MHz output is a
square wave with an output level equal to VDD.
Block Diagram
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