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參數(shù)資料
| 型號： | LC8213 |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | QIP-80 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 174K |
| 代理商： | LC8213 |
LC8213
No.4605–6/10
Others
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Explanation of Function
Coding method
The coding method follows the CCITT T.4, T.6 MH, MR and MMR coding methods that are the standard for the G3 and
G4 facsimiles.
Processing mode
A maximum of 64k lines for processing can be set, and processing per block is possible. Processing per line is also
possible. The coding and decoding FIFOs are built-in, and coding and decoding can be performed alternately for several
lines at a time.
When coding, the LC8213 reads the image data in order from the start address of the image memory set in the register.
This data is coded and written into the coding FIFO. When the set number of lines have been processed, the CPU is
interrupted.
When decoding, the LC8213 reads the coded data from the decoding FIFO, reproduces the image data, and writes it into
the image memory. When the set number of lines have been processed or a decoding error occurs, the CPU is inter-
rupted.
Line skip mode
This mode allows the coded amount of blank lines to be decreased to half of the minimum transmission bits. The line
skip bit (blank line judgement bit) is added to the end of the EOL code, and a fill bit is added to the blank line so that the
coded amount is half of the minimum transmission bits. For lines that are not completely blank, the normal codes are
transmitted after the line skip bit.
CPU interface
This interface has an 8-bit data bus, and various operation modes can be set by accessing the interface register. As
interface terminals for the external DMA controller are built-in, DMA transfer between the LC8213 and the CPU bus
memory is possible.
Image memory interface
The image memory address space has 16M bytes.
The data bus size can be selected from 8-bit or 16-bit.
DMA transfer function
DMA transfer is performed between the image memory and I/O device with the internal DMA controller. A maximum
of 64k lines can be set for transferring.
Data transfer function
Data transfer can be performed without coding/decoding between the CPU bus and image memory bus.
Pad bit processing
Pad bit processing can be selected. Pad bit processing is a function that outputs a “0” after 1 line of coded data so that it
is an 8-bit unit.
Parameter settings
The following parameters can be set to the listed values.
No. of processing bits per line (byte unit)
1 to 8k bytes
Document width (byte unit)
1 to 8k bytes
No. of processing lines
1 to 64k
Minimum transmission bits per line
0 to 64k
K parameters during MR coding
0 to 64k
No. of processing lines for DMA transfer
1 to 64k
No. of EOL that structure RTC code
0 to 255
The document width and no. of processing bits per line can be set separately, so a part of the document can be cut
and coded or decoded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC8213K | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Image Data Compression/Expansion Processor |
| LC8214 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Facsimile Controller |
| LC82141 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Facsimile Controller |
| LC82150 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS LSI |
| LC82151 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip Facsimile Controller |
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