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參數(shù)資料
| 型號： | LC866524A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四2正輸入或門 14-TSSOP封裝；-40℃到85℃ |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 641K |
| 代理商： | LC866524A |
LC866548/40/32/28/24A
No.6700-4/21
(14) Multiplication and division
- 16 bit
×
8 bit (7 instruction cycle times)
- 16 bit ÷ 8 bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit used for the system clock
- On-chip CF oscillation circuit used for the system clock
- On-chip Crystal oscillation circuit used for the system clock and for time-base clock
Note : External resisters (Rf, Rd) are required
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to stop all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
Reset terminal (
RES
) set to low level.
Input a assigned level to P70/INT0/T0IN or P71/INT1/T0IN terminal.
Input a Port0 interrupt condition.
(17) Factory shipment
QFP100E delivery form
(18) Development Tools
- Evaluation chip
: LC866094
- EPROM version
: LC86E6548
- One time version
: LC86P6548
- Emulator
: EVA86000 + ECB866500 (Evaluation chip board) + POD866500 (Pod)
Notes for use
Follow the under table.
Frequency range of the system clock
Voltage range
15kHz to 3MHz
30kHz to 6MHz
Internal RC oscillation
Clock Divider
1/1
1/1, 1/2
1/1, 1/2
Note
Can not use 1/2 divider
4.5V to 6.0V
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