參數(shù)資料
型號(hào): LC876662B
廠商: Sanyo Electric Co.,Ltd.
英文描述: RF CONNECTOR; 50 OHM REVERSE POLARITY BNC MALE RIGHT ANGLE, CLAMP ATTACHMENT FOR RG59 & RG62; *MEETS FCC PART 15.203 REQUIREMENTS*
中文描述: 8位單片機(jī)
文件頁數(shù): 7/23頁
文件大?。?/td> 655K
代理商: LC876662B
LC876694B/78B/62B
No.6843-7/23
Pin Assignment
Pin name
VSS1
VSS2
I/O
-
Function
Option
No
Power supply (-)
VDD1
VDD2
VDD3
VDD4
VP
PORT0
P00 to P07
-
Power supply (+)
No
-
Power supply (-)
8bit input/output port
data direction programmable in nibble units
Use of pull-up resistor can be specified in nibble units
Input for HOLD release
Input for port 0 interrupt
15V withstand at N-channel open drain output
8bit input/output port
data direction programmable for each bit
Use of pull-up resistor can be specified for each bit
Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
8bit Input/output port
Data direction can be specified for each bit
Use of pull-up resistor can be specified for each bit
15V withstand at N-channel open drain output
4bit Input/output port
Data direction can be specified for each bit
Use of pull-up resistor can be specified for each bit
Other functions
P70: INT0 input/HOLD release input/Timer0L capture Input/output for watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/High
speed clock counter input
P73: INT3 input(noise rejection filter attached input)/timer 0 event input/Timer 0H
capture input
AD input port: AN8(P70), AN9(P71)
The following types of interrupt detection are possible:
No
Yes
I/O
PORT1
P10 to P17
I/O
Yes
PORT3
P30 to P33
I/O
Yes
Rising
Falling
Rising/
falling
No
No
Yes
Yes
H level
L level
INT0
INT1
INT2
INT3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
PORT7
P70 to P73
I/O
No
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