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參數(shù)資料
| 型號： | LE79R251JC |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 533K |
| 代理商： | LE79R251JC |
P R E L I M I N A R Y
16
Le79R251 ISLIC Data Sheet
Thermal-Management Equations
Applies to all Modes except Standby and Ringing which have no thermal management:
TIMING SPECIFICATIONS
Note:
1.
The P1
–
3 pins are updated continuously during operation by the LD signal.
2.
After a power-on reset or hardware reset, the relay outputs from the Le79R251 device turn all relays off. An unassuming state is to place
the relay control pins, which are level triggered, to a reset state for all relays. Any noise encountered only raises the levels toward the register
lock state.
3.
When writing to the ISLIC registers, the sequence is:
a)
b)
c)
d)
Set LD pin to mid-state
Place appropriate data on the P1
–
3 pins
Assert the LD pin to High or Low to write the proper data
Return LD pin to mid-state
Le79R251 device registers are refreshed at 5.33 kHz when used with an ISLAC device.
4.
5.
If the clock or MPI becomes disabled, the LD pins and P1
–
3 returns to 0 V state, thus protecting the Le79R251 device and the line
connection.
6.
Not tested in production. Guaranteed by characterization.
I
L
< 7.5 mA
P
SLIC
= (S
BAT
– I
L
(R
L
+ 2R
FUSE
)) I
L
+ 0.3 W
PT
RTMG
= 0
TMG resistor-current is limited to be 7.5 mA < I
L
. If I
L
< 7.5 mA,
no current flows in the TMG resistor and it all flows in the
Le79R251.
I
L
> 7.5 mA
R
TMG
= (S
BAT
– I
L
(R
L
+ 2R
FUSE
)) / (2(I
L
– 7.5 mA))
P
SLIC
= I
L
(S
BAT
– I
L
(R
L
+ 2R
FUSE
)) + 0.3 W – PT
RTMG
PT
RTMG
= (I
L
– 7.5 mA)
2
(2R
TMG
)
These equations are valid when
R
TMG
(I
L
– 7.5 mA) < (S
BAT
– (R
F
+ R
L
)I
L
) / 2 – 2
because the longitudinal voltage is one-half the battery voltage
and the TMG switches require approximately 2 V.
To choose a power rating for RTMG:
P
RATING
> PT
RTMG
/ 2
Note that for reliable operation, P
SLIC
should be less than
1.33 W.
Symbol
Signal
Parameter
Min
Typ
Max
Unit
trSLD
LD
Rise time Le79R251 device LD pin
2
μs
tfSLD
LD
Fall time Le79R251 device LD pin
2
tSLDPW
LD
LD minimum pulse width
3
tSDXSU
P1,P2,P3
P1–3 data Setup time
4.5
tSDXHD
P1,P2,P3
P1–3 data hold time
4.5
tSDXD
P1,P2,P3
Max P1–3 data delay
5
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