參數(shù)資料
型號: LFEC1E-3TN100I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 112/163頁
文件大?。?/td> 0K
描述: IC FPGA 1.5KLUTS 67I/O 100-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: EC
邏輯元件/單元數(shù): 1500
RAM 位總計(jì): 18432
輸入/輸出數(shù): 67
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
其它名稱: 220-1769
LFEC1E-3TN100I-ND
3-16
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Internal Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
PFU/PFF Logic Mode Timing
tLUT4_PFU
LUT4 Delay (A to D Inputs to F Output)
0.25
0.31
0.36
ns
tLUT6_PFU
LUT6 Delay (A to D Inputs to OFX Output)
0.40
0.48
0.56
ns
tLSR_PFU
Set/Reset to Output of PFU
0.81
0.98
1.14
ns
tSUM_PFU
Clock to Mux (M0,M1) Input Setup Time
0.12
0.14
0.16
ns
tHM_PFU
Clock to Mux (M0,M1) Input Hold Time
-0.05
-0.06
-0.06
ns
tSUD_PFU
Clock to D Input Setup Time
0.12
0.14
0.16
ns
tHD_PFU
Clock to D Input Hold time
-0.03
-0.03
-0.04
ns
tCK2Q_PFU
Clock to Q Delay, D-type Register Configuration
0.36
0.44
0.51
ns
tLE2Q_PFU
Clock to Q Delay Latch Configuration
0.48
0.58
0.68
ns
tLD2Q_PFU
D to Q Throughput Delay when Latch is Enabled
0.50
0.60
0.69
ns
PFU Dual Port Memory Mode Timing
tCORAM_PFU
Clock to Output
0.36
0.44
0.51
ns
tSUDATA_PFU
Data Setup Time
-0.20
-0.24
-0.28
ns
tHDATA_PFU
Data Hold Time
0.26
0.31
0.36
ns
tSUADDR_PFU
Address Setup Time
-0.51
-0.62
-0.72
ns
tHADDR_PFU
Address Hold Time
0.64
0.77
0.90
ns
tSUWREN_PFU
Write/Read Enable Setup Time
-0.24
-0.29
-0.34
ns
tHWREN_PFU
Write/Read Enable Hold Time
0.30
0.36
0.42
ns
PIC Timing
PIO Input/Output Buffer Timing
tIN_PIO
Input Buffer Delay
0.56
0.67
0.78
ns
tOUT_PIO
Output Buffer Delay
1.92
2.31
2.69
ns
IOLOGIC Input/Output Timing
tSUI_PIO
Input Register Setup Time (Data Before Clock)
0.90
1.08
1.26
ns
tHI_PIO
Input Register Hold Time (Data after Clock)
0.62
0.74
0.87
ns
tCOO_PIO
Output Register Clock to Output Delay
0.33
0.40
0.46
ns
tSUCE_PIO
Input Register Clock Enable Setup Time
-0.10
-0.12
-0.14
ns
tHCE_PIO
Input Register Clock Enable Hold Time
0.12
0.14
0.17
ns
tSULSR_PIO
Set/Reset Setup Time
0.18
0.21
0.25
ns
tHLSR_PIO
Set/Reset Hold Time
-0.15
-0.18
-0.21
ns
EBR Timing
tCO_EBR
Clock to Output from Address or Data
3.64
4.37
5.10
ns
tCOO_EBR
Clock to Output from EBR output Register
0.74
0.88
1.03
ns
tSUDATA_EBR
Setup Data to EBR Memory
-0.29
-0.35
-0.41
ns
tHDATA_EBR
Hold Data to EBR Memory
0.37
0.44
0.52
ns
tSUADDR_EBR
Setup Address to EBR Memory
-0.29
-0.35
-0.41
ns
tHADDR_EBR
Hold Address to EBR Memory
0.37
0.45
0.52
ns
tSUWREN_EBR
Setup Write/Read Enable to EBR Memory
-0.18
-0.22
-0.26
ns
tHWREN_EBR
Hold Write/Read Enable to EBR Memory
0.23
0.28
0.33
ns
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