參數(shù)資料
型號： LFEC1E-4QN208C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 94/163頁
文件大小： 0K
描述： IC FPGA 1.5KLUTS 208PQFP
標準包裝： 48
系列： EC
邏輯元件/單元數(shù)： 1500
RAM 位總計： 18432
輸入/輸出數(shù)： 112
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-PQFP（28x28）
2-33
Architecture
LatticeECP/EC Family Data Sheet
Oscillator
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura-
tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2-
15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro-
cess, the following sequence takes place:
1.
User selects a different Master Clock frequency.
2.
During configuration the device starts with the default (2.5MHz) Master Clock frequency.
3.
The clock configuration settings are contained in the early configuration bit stream.
4.
The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
For further information about the use of this oscillator for configuration, please see the list of technical documenta-
tion at the end of this data sheet.
Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
CCLK (MHz)
2.5*
13
45
4.3
15
51
5.4
20
55
6.9
26
60
8.1
30
130
9.2
34
—
10.0
41
—
相關PDF資料
PDF描述
VI-26Y-CY-S CONVERTER MOD DC/DC 3.3V 33W
VI-26Y-CX-S CONVERTER MOD DC/DC 3.3V 49.5W
ECC05DRXH-S734 CONN EDGECARD 10POS DIP .100 SLD
MC7815ECTBU IC REG LDO 15V 1A TO-220
KA7815E IC REG LDO 15V 1A TO-220
相關代理商/技術參數(shù)
參數(shù)描述
LFEC1E-4QN208I 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.5K LUTs 112 IO 1.2 V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC1E-4T100C 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.5K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC1E-4T100CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.5 LUT 67 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC1E-4T100I 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.5K LUTs 67 IO 1.2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC1E-4T100IES 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.5 LUT 67 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*