Table 2-7. Maximum Number of Elements in a Block Some options are available in four elements." />
參數(shù)資料
型號： LFEC1E-4QN208I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 75/163頁
文件大?。?/td> 0K
描述： IC FPGA 1.5KLUTS 208PQFP
標(biāo)準(zhǔn)包裝： 48
系列： EC
邏輯元件/單元數(shù)： 1500
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 112
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
2-16
Architecture
LatticeECP/EC Family Data Sheet
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the
‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly
by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and
subtraction on every cycle.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-19 shows the MULT sysDSP element.
Figure 2-19. MULT sysDSP Element
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC
sysDSP element.
Width of Multiply
x9
x18
x36
MULT
841
MAC
2
—
MULTADD
4
2
—
MULTADDSUM
2
1
—
Multiplier
x
n
m
n
m
n
m
n
m
m+n
(default)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Pipeline
Register
Input
Register
Multiplier
Multiplicand
Signed
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Input Data
Register A
Input Data
Register B
Output
Register
To
Multiplier
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