參數(shù)資料
型號： LFEC33E-3FN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 81/163頁
文件大?。?/td> 0K
描述： IC FPGA 32.8KLUTS 360I/O 484-BGA
標準包裝： 60
系列： EC
邏輯元件/單元數(shù)： 32800
RAM 位總計： 434176
輸入/輸出數(shù)： 360
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應商設備封裝： 484-FPBGA（23x23）
2-21
Architecture
LatticeECP/EC Family Data Sheet
For further information about the sysDSP block, please see the list of technical information at the end of this data
sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as
shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O
buffer, and receives input from the buffer.
Figure 2-24. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16
PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
PIO B
PADA
"T"
PADB
"C"
OPOS0
ONEG0
OPOS1
ONEG1
TD
INCK
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
PIO A
sysIO
Buffer
DQS
DDRCLKPOL
IOLD0
IOLT0
D0
DDRCLK
DI
IPOS1
IPOS0
INCK
INDD
INFF
D0
D1
TD
D1
Output
Register Block
(2 Flip Flops)
Tristate
Register Block
(2 Flip Flops)
DDRCLK
Input
Register Block
(5 Flip Flops)
CLKO
CLKI
CEO
CEI
Control
Muxes
LSR
GSR
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相關代理商/技術參數(shù)
參數(shù)描述
LFEC33E-3FN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs 360 IO 1. 2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC33E-3FN672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC33E-3FN672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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LFEC33E-3Q208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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