參數(shù)資料
型號: LFEC33E-5F672C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: LatticeECP/EC Family Data Sheet
中文描述: FPGA, 4096 CLBS, 32800 GATES, 420 MHz, PBGA672
封裝: 27 X 27 MM, FPBGA-672
文件頁數(shù): 65/117頁
文件大小: 557K
代理商: LFEC33E-5F672C
4-3
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
PIO Within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
Data (DQ) Pins
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering de
fi
nitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.
相關PDF資料
PDF描述
LFECP33E-5F672C LatticeECP/EC Family Data Sheet
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LFECP1E-5F672I LatticeECP/EC Family Data Sheet
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