Figure 2-34. LatticeECP/EC Banks LatticeECP/EC devices contain two types of sysI/O buffer pai" />
參數(shù)資料
型號： LFEC3E-3TN144I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 90/163頁
文件大?。?/td> 0K
描述： IC FPGA 3.1KLUTS 97I/O 144-TQFP
標(biāo)準(zhǔn)包裝： 60
系列： EC
邏輯元件/單元數(shù)： 3100
RAM 位總計： 56320
輸入/輸出數(shù)： 97
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： 220-1776
LFEC3E-3TN144I-ND
2-29
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-34. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysI/O buffer pairs.
1.
Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers
and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot
socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid
operating levels and the device has been configured.
2.
Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers. See the IDK specification for I/O leakage cur-
rent during power-up.
V
REF1(2)
GND
Bank
2
V
CCIO2
V
REF2(2)
V
REF1(3)
GND
Bank
3
V
CCIO3
V
REF2(3)
V
REF1(7)
GND
TOP
LEFT
RIGHT
BOTTOM
Bank
7
V
CCIO7
V
REF2(7)
V
REF1(6)
GND
Bank
6
V
CCIO6
V
REF2(6)
V
REF1(5)
GND
Bank 5
V
CCIO5
V
REF2(5)
V
REF1(4)
GND
Bank 4
V
CCIO4
V
REF2(4)
V
REF1(0)
GND
Bank 0
V
CCIO0
V
REF2(0)
V
REF1(1)
GND
Bank 1
V
CCIO1
V
REF2(1)
相關(guān)PDF資料
PDF描述
ECM06DSEF-S243 CONN EDGECARD 12POS .156 EYELET
TAP686M016SRW CAP TANT 68UF 16V 20% RADIAL
V24B3V3T150BF2 CONVERTER MOD DC/DC 3.3V 150W
EEM24DTBN-S189 CONN EDGECARD 48POS R/A .156 SLD
EEM24DTBH-S189 CONN EDGECARD 48POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC3E-4F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F256CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 160 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 1.2V -4 Sp d I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F256IES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 160 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-4F484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*