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參數資料
| 型號： | LFEC3E-5F256I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | LatticeECP / EC的系列數據手冊 |
| 文件頁數： | 11/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC3E-5F256I |
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2-8
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LFEC3E-5F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC3E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC3E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC3E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC3E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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