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參數(shù)資料
| 型號(hào)： | LFEC3E-5TN144C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 2/163頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.1KLUTS 97I/O 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | EC |
| 邏輯元件/單元數(shù)： | 3100 |
| RAM 位總計(jì)： | 56320 |
| 輸入/輸出數(shù)： | 97 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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2-7
Architecture
LatticeECP/EC Family Data Sheet
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered, the routing of both short and long connections between PFUs.
The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally,
the place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
Clock Input
PLL Input
Clock Input
PLL Input
From Routing
Clock Input
From Routing
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Note: Smaller devices have two PLLs.
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| AT88SC018-SU-CN | IC CRYPTOCOMPANION RF/MEM 8SOIC |
| LFEC3E-3FN256I | IC FPGA 3.1KLUTS 256FPBGA |
| LFXP3E-3T144C | IC FPGA 3.1KLUTS 100I/O 144-TQFP |
| RMC60DRES-S93 | CONN EDGECARD 120PS .100 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC3E-5TN144I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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