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參數(shù)資料
| 型號： | LFEC40E-4F672C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | FPGA, 5120 CLBS, PBGA672 |
| 封裝： | 27 X 27 MM, FPBGA-672 |
| 文件頁數(shù)： | 63/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC40E-4F672C |
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www.latticesemi.com
4-1
Pinout Information_01.2
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During con
fi
guration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
con
fi
guration.
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
as assigned V
REF
inputs. When not used, they may be used as I/O pins.
10K ohm +/-1% resistor must be connected between this pad and ground.
GSRN
NC
GND
V
CC
I
—
—
—
V
CCAUX
—
V
CCIOx
—
V
REF1_x,
V
REF2_x
—
XRES
PLL and Clock Functions
(Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be con
fi
gured to be output.
Test and Programming
(Dedicated pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during con
fi
guration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
—
[LOC][num]_PLL[T, C]_IN_A
I
[LOC][num]_PLL[T, C]_FB_A
I
PCLK[T, C]_[n:0]_[3:0]
I
[LOC]DQS[num]
I
TMS
I
TCK
I
LatticeECP/EC Family Data Sheet
Pinout Information
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC40E-4F672I | LatticeECP/EC Family Data Sheet |
| LFEC40E-4F900I | LatticeECP/EC Family Data Sheet |
| LFEC40E-4Q208I | LatticeECP/EC Family Data Sheet |
| LFEC40E-4T100I | LatticeECP/EC Family Data Sheet |
| LFEC40E-4T144C | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC40E-4F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-4F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-4F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-4Q208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-4Q208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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