- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377633 > LFEC6E-5F484I (Lattice Semiconductor Corporation) Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | LFEC6E-5F484I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85 |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 3/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC6E-5F484I |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
1-2
Introduction
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost.
For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an ef
fi
cient FPGA
fabric with high-speed dedicated functions. Lattice’s
fi
rst family to implement this approach is the LatticeECP-DSP
(EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC (ECon-
omy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to
achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER
ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn-
thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its
fl
oor planning
tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the
routing and back-annotates it into the design for timing veri
fi
cation.
design tool from Lattice allows large complex designs to be ef
fi
ciently implemented using the Latti-
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC6E-5F900I | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85 |
| LFEC6E-5T100C | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85 |
| LFEC6E-5T100I | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85 |
| LFECP33E-4F256I | 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Single Ch. Pseudo-differential 8-SOIC -40 to 85 |
| LFECP33E-4F484C | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC6E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC6E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC6E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC6E-5F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC6E-5FN256C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。