Table 2-7. Maximum Number of Elements in a Block Some options are available in four elements." />
參數資料
型號： LFECP10E-4FN256C
廠商： Lattice Semiconductor Corporation
文件頁數： 75/163頁
文件大?。?/td> 0K
描述： IC FPGA 10.2KLUTS 195I/O 256-BGA
標準包裝： 90
系列： ECP
邏輯元件/單元數： 10200
RAM 位總計： 282624
輸入/輸出數： 195
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應商設備封裝： 256-FPBGA（17x17）
2-16
Architecture
LatticeECP/EC Family Data Sheet
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the
‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly
by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and
subtraction on every cycle.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-19 shows the MULT sysDSP element.
Figure 2-19. MULT sysDSP Element
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC
sysDSP element.
Width of Multiply
x9
x18
x36
MULT
841
MAC
2
—
MULTADD
4
2
—
MULTADDSUM
2
1
—
Multiplier
x
n
m
n
m
n
m
n
m
m+n
(default)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Pipeline
Register
Input
Register
Multiplier
Multiplicand
Signed
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Input Data
Register A
Input Data
Register B
Output
Register
To
Multiplier
相關PDF資料
PDF描述
LFECP10E-3F256I IC FPGA 10.2KLUTS 195I/O 256-BGA
LFXP10E-3F388C IC FPGA 9.7KLUTS 244I/O 388-BGA
LFXP10E-3FN388C IC FPGA 9.7KLUTS 388FPBGA
LFXP10C-3F388C IC FPGA 9.7KLUTS 244I/O 388-BGA
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相關代理商/技術參數
參數描述
LFECP10E-4FN256I 功能描述:FPGA - 現場可編程門陣列 10.2K LUTs 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-4FN484C 功能描述:FPGA - 現場可編程門陣列 10.2K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-4FN484I 功能描述:FPGA - 現場可編程門陣列 10.2K LUTs 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-4FN672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-4FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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