參數資料
型號： LFECP15E-5T144C
廠商： Lattice Semiconductor Corporation
英文描述： Enhanced Product 12-Bit Analog-To-Digital Converter W/ Serial Control And 11 Analog Input 20-SOIC -40 to 125
中文描述： LatticeECP / EC的系列數據手冊
文件頁數： 29/117頁
文件大?。?/td> 557K
代理商： LFECP15E-5T144C
2-26
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-30. Tristate Register Block
Control Logic Block
The control logic block allows the selection and modi
fi
cation of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the EC devices
provide this capability. In addition to these registers, the EC devices contain two elements to simplify the design of
input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-
ing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync
registers in the input register blocks. Figures 2-31 and 2-32 show how the DQS transition signals are routed to the
PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-32. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
D
LE*
Q
D
D-Type
/LATCH
Q
ONEG1
CLK1
Programmed
Control
TO
Latch
*Latch is transparent when input is low.
OPOS1
OUTDDN
0
1
0
1
From
Routing
To sysIO
Buffer
TD
相關PDF資料
PDF描述
LFECP15E-5T144I Enhanced Product 12-Bit Analog-To-Digital Converter W/ Serial Control And 11 Analog Input 20-SSOP -55 to 125
LFECP1E-5F484C Automotive Catalog 12-Bit Analog-to-Digital Converters With Serial Control and 11 Analog Inputs 20-SSOP -40 to 85
LFECP1E-5F484I Automotive Catalog 12-Bit Analog-to-Digital Converters With Serial Control and 11 Analog Inputs 20-SSOP -40 to 85
LFECP1E-5T100C LatticeECP/EC Family Data Sheet
LFECP1E-5T100I LatticeECP/EC Family Data Sheet
相關代理商/技術參數
參數描述
LFECP15E-5T144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP15E-5TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP15E-5TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP15E-5TN144C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP15E-5TN144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*