參數(shù)資料
型號(hào)： LFECP20E-3T144I
廠商： Lattice Semiconductor Corporation
英文描述： LatticeECP/EC Family Data Sheet
中文描述： LatticeECP / EC的系列數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù)： 21/117頁(yè)
文件大小： 557K
代理商： LFECP20E-3T144I
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2-18
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-21. MULTADDSUM
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be
fi
lled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most signi
fi
cant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Multiplier
x
Add/Sub0
n
m
m+n
(default)
m+n
(default)
m+n+1
m+n+2
m+n+2
m+n+1
m+n
(default)
m+n
(default)
m
n
m
n
m
n
n
m
x
n
n
m
n
n
m
Multiplier
x
Multiplier
Multiplier
x
Add/Sub1
n
m
m
n
m
n
m
n
n
m
n
m
m
n
m
n
n
m
SUM
Multiplier B0
Multiplicand A0
Multiplier B1
Multiplicand A1
Multiplier B2
Multiplicand A2
Multiplier B3
Multiplicand A3
Signed
Shift Register B In
Output
Addn0
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
To Add/Sub0
To Add/Sub0, Add/Sub1
Pipeline
Register
Pipeline
Register
Input
Register
To Add/Sub1
Addn1
Pipeline
Register
Pipeline
Register
Pipeline
Register
Shift Register A In
Shift Register B Out
Shift Register A Out
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register B
Input Data
Register B
Input Data
Register B
Input Data
Register B
O
R
相關(guān)PDF資料
PDF描述
LFECP20E-4F256C LatticeECP/EC Family Data Sheet
LFECP20E-4F256I LatticeECP/EC Family Data Sheet
LFECP20E-4F484C 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Single Ch. 8-SOIC -40 to 85
LFECP20E-4F672C 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Single Ch. 8-MSOP -40 to 85
LFECP20E-4F672I LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP20E-3TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-3TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-3TN144C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-3TN144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-4F256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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