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參數資料
| 型號： | LFECP20E-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Dual Ch. Auto Sweep 8-MSOP -40 to 85 |
| 中文描述： | FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, FPBGA-484 |
| 文件頁數： | 11/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP20E-5F484C |
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2-8
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
相關PDF資料 |
PDF描述 |
|---|---|
| LFECP20E-5F484I | LatticeECP/EC Family Data Sheet |
| LFECP20E-5F672I | 12-bit, 400 KSPS ADC, 4-Ch. Serial With Powerdown 16-SOIC 0 to 70 |
| LFECP20E-5F900I | LatticeECP/EC Family Data Sheet |
| LFECP20E-5T100C | LatticeECP/EC Family Data Sheet |
| LFECP20E-5T100I | 12-bit, 400 KSPS ADC, 4-Ch. Serial With Powerdown 16-TSSOP -40 to 85 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LFECP20E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP20E-5F672C | 功能描述:FPGA - 現場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP20E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP20E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP20E-5F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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