參數(shù)資料
型號： LFECP33E-3FN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 68/163頁
文件大?。?/td> 0K
描述： IC FPGA 32.8KLUTS 360I/O 484-BGA
產(chǎn)品培訓(xùn)模塊： LatticeECP3 Introduction
標準包裝： 60
系列： ECP
邏輯元件/單元數(shù)： 32800
RAM 位總計： 434176
輸入/輸出數(shù)： 360
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
2-13
Architecture
LatticeECP/EC Family Data Sheet
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1.
Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2.
Write Through – a copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
3.
Read-Before-Write – when new data is being written, the old content of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-16.
EBR
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
DO[35:0]
Single Port RAM
EBR
True Dual Port RAM
Pseudo-Dual Port RAM
ROM
AD[12:0]
CLK
CE
DO[35:0]
RST
CS[2:0]
EBR
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CLKB
CEB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADW[12:0]
DI[35:0]
CLKW
CEW
ADR[12:0]
DO[35:0]
CER
CLKR
WE
RST
CS[2:0]
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LFECP33E-3FN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP33E-3FN672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP33E-3FN672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 32.8K LUTs 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP33E-3Q208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP33E-3Q208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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