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      1. 參數(shù)資料
        型號: LFECP3E-5T144C
        廠商: Lattice Semiconductor Corporation
        英文描述: Dual uPower Low-Voltage Operational Amplifier 8-SOIC
        中文描述: LatticeECP / EC的系列數(shù)據(jù)手冊
        文件頁數(shù): 10/117頁
        文件大小: 557K
        代理商: LFECP3E-5T144C
        2-7
        Architecture
        Lattice Semiconductor
        LatticeECP/EC Family Data Sheet
        Routing
        There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
        related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
        segments.
        The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
        The x1 and x2 connections provide fast and ef
        fi
        cient connections in horizontal and vertical directions. The x2 and
        x6 resources are buffered allowing both short and long connections routing between PFUs.
        The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
        place and route tool is completely automatic, although an interactive routing editor is available to optimize the
        design.
        Clock Distribution Network
        The clock inputs are selected from external I/O, the sysCLOCK PLLs or routing. These clock inputs are fed
        through the chip via a clock distribution system.
        Primary Clock Sources
        LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
        LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
        are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
        Figure 2-6. Primary Clock Sources
        From Routing
        Clock Input
        From Routing
        PLL Input
        Clock Input
        PLL Input
        PLL Input
        Clock Input
        PLL Input
        From Routing
        Clock Input
        From Routing
        PLL
        PLL
        PLL
        PLL
        20 Primary Clock Sources
        To Quadrant Clock Selection
        Note: Smaller devices have two PLLs.
        相關PDF資料
        PDF描述
        LFECP3E-5T144I LatticeECP/EC Family Data Sheet
        LFECP40E-3F256C LatticeECP/EC Family Data Sheet
        LFECP40E-3F256I LatticeECP/EC Family Data Sheet
        LFECP40E-3F484C Dual uPower Low-Voltage Operational Amplifier 8-PDIP
        LFECP40E-3F484I LatticeECP/EC Family Data Sheet
        相關代理商/技術參數(shù)
        參數(shù)描述
        LFECP3E-5T144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
        LFECP40E-3F256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
        LFECP40E-3F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
        LFECP40E-3F484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
        LFECP40E-3F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet