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參數(shù)資料

型號：	LFECP6E-3FN484C
廠商：	Lattice Semiconductor Corporation
文件頁數(shù)：	87/163頁
文件大?。?/td>	0K
描述：	IC FPGA 6.1KLUTS 484FPBGA
標(biāo)準(zhǔn)包裝：	60
系列：	ECP
邏輯元件/單元數(shù)：	6100
RAM 位總計：	94208
輸入/輸出數(shù)：	224
電源電壓：	1.14 V ~ 1.26 V
安裝類型：	表面貼裝
工作溫度：	0°C ~ 85°C
封裝/外殼：	484-BBGA
供應(yīng)商設(shè)備封裝：	484-FPBGA（23x23）

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Introduction

LatticeECP/EC Family Data Sheet

Introduction

The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For

maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA

fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-

DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC

(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function

blocks to achieve lower cost solutions.

The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical

FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.

Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-

alent in cost-sensitive applications.

The ispLEVER

design tool suite from Lattice allows large complex designs to be efficiently implemented using the

LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis

tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to

place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing

and back-annotates it into the design for timing verification.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE modules for the LatticeECP/EC

family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their

design, increasing their productivity.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
LFECP6E-3FN484I	功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 224 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3FN672C	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3FN672I	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3Q208C	功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 147 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3Q208I	功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 147 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

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