參數(shù)資料
型號: LFX200B-04FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 76/119頁
文件大?。?/td> 0K
描述: IC FPGA 210KGATES 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 2704
RAM 位總計: 113664
輸入/輸出數(shù): 160
門數(shù): 210000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
2
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today’s system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the sys-
HSI Block.
Electrically Erasable CMOS (E
2CMOS) memory cells provide the ispXPGA family with non-volatile capability.
These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-
tions. This capability also means that expensive external configuration memories are not required and that designs
can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if
desired. Both the SRAM and E
2CMOS cells can be programmed and verified through the IEEE 1532 industry stan-
dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG peripheral port.
The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M func-
tional gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies,
providing easy integration into the overall system.
System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-
ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization
(SERDES).
The ispLEVER design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-
thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these
common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor
planning and the management of other constraints within the device. The tool also provides outputs to common
timing analysis tools for timing analysis.
To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the
ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using
pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,
and memory controllers.
Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-
ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.
Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly
used by logic designers.
Table 2. ispXPGA Speed Performance for Typical Building Blocks
Function
Performance
8:1 Asynch MUX
150 MHz
1:32 Asynch Demultiplexer
125 MHz
8 x 8 2-LL Pipelined Multiplier
225 MHz
32-bit Up/Down Counter
290 MHz
32-bit Shift Register
360 MHz
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
RF803E IC ENCODER 3 DGTL I/O 8-PDIP
DS9100-B+ CONTACT TOUCH AND HOLD
LFEC33E-4FN484I IC FPGA 32.8KLUTS 484FPBGA
LFEC33E-5FN484C IC FPGA 32.8KLUTS 484FPBGA
RSC49DRTH-S93 CONN EDGECARD 98POS DIP .100 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX200B-04FN516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 210K Gt ispJTAG 2.5 /3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-04FN516C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-05F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 210K Gates, 160 I/O 2.5/3.3V, -5 speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-05F516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 210K 208 I/O ispJTAG RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200B-05FH516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LFX200B-05F516C RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256