Lattice Semiconductor
ispXPGA Family Data Sheet
29
ispXPGA EBR Timing Parameters
Parameter
Description
-4
-3
Units
Min.
Max.
Min.
Max.
Synchronous Write
t
EBSWAD_S
t
EBSWAD_H
t
EBSWCPW
t
EBSWWE_S
t
EBSWWE_H
t
EBSWD_S
t
EBSWD_H
Synchronous Read
Address Setup Delay
0.61
—
0.70
—
ns
Address Hold Delay
-0.39
—
-0.33
—
ns
Clock Pulse Width
—
3.40
—
3.91
ns
Write Enable Setup Time
-0.12
—
-0.10
—
ns
Write Enable Hold Time
0.16
—
0.18
—
ns
Data Setup Time
0.28
—
0.32
—
ns
Data Hold Time
-0.26
—
-0.22
—
ns
t
EBSR_CO
t
EBSRAD_S
t
EBSRAD_H
t
EBSRCPW
t
EBSRCE_S
t
EBSRCE_H
t
EBSRWE_S
t
EBSRWE_H
t
EBSRWEEN
t
EBSRWEDIS
t
EBSREN
t
EBSRDIS
Asynchronous Read
Clock to Data Delay
—
2.19
—
2.52
ns
Address Setup Delay
0.10
—
0.12
—
ns
Address Hold Delay
-0.07
—
-0.06
—
ns
Clock Pulse Width
—
3.40
—
3.91
ns
Clock Enable Setup Time
-1.71
—
-1.45
—
ns
Clock Enable Hold Time
1.69
—
1.94
—
ns
Write Enable Setup Time
-0.17
—
-0.14
—
ns
Write Enable Hold Time
0.12
—
0.14
—
ns
Write Enable to Data Enable Time
—
1.05
—
1.21
ns
Write Enable to Data Disable Time
—
1.02
—
1.17
ns
Output Enable to Data Enable Time
—
1.05
—
1.21
ns
Output Enable to Data Disable Time
—
0.86
—
0.99
ns
t
EBARADO
t
EBARAD_H
t
EBARWEEN
t
EBARWEDIS
t
EBAREN
t
EBARDIS
Address to New Valid Data Delay
—
2.46
—
2.83
ns
Address to Previous Valid Data Delay
—
2.17
—
2.50
ns
Write Enable to Data Enable Time
—
1.04
—
1.20
ns
Write Enable to Data Disable Time
—
1.01
—
1.16
ns
Output Enable to Data Enable Time
—
1.05
—
1.21
ns
Output Enable to Data Disable Time
—
0.86
—
0.99
ns
Timing v.2.0