HDL Synthesis Coding Guidelines
Lattice Semiconductor
for Lattice Semiconductor FPGAs
15-9
sis Library. The definitions of these library elements can be found in the Reference Manuals section of the isp-
LEVER on-line help system.
Logic gates and LUTs
Comparators, adders, subtractors
Counters
Flip-flops and latches
Memory, 4E-specific memory (block RAM function)
Multiplexors
Multipliers
All I/O cells, including I/O flip-flops
PIC cells
Special cells, including PLL, GSR, boundary scan, etc.
FPSC elements
IPepxress, a parameterized module complier optimized for Lattice FPGA devices, is available for more complex
logic functions. IPexpress supports generation of library elements with a number of different options such as PLLs
and creates parameterized logic functions such as PFU and EBR memory, multipliers, adders, subtractors, and
counters. IPexpress accepts options that specify parameters for parameterized modules such as data path mod-
ules and memory modules, and produces a circuit description with Lattice Semiconductor FPGA library elements.
Output from IPexpress can be written in EDIF, VHDL, or Verilog. In order to use synthesis tools to utilize the Lattice
FPGA architectural features, it is strongly recommended to use IPexpress to generate modules for source code
instantiation. The following are examples of Lattice Semiconductor FPGA modules supported by IPexpress:
PLL
Memory implemented in PFU:
– Synchronous single-port RAM, synchronous dual-port RAM, synchronous ROM, synchronous FIFO
Memory implemented with EBR:
– Quad-port Block RAM, Dual-Port Block RAM, Single-Port Block RAM, ROM, FIFO
Other EBR based Functions
– Multiplier, CAM
PFU based functions
– Multiplier, adder, subtractor, adder/subtractor, linear feedback shifter, counter
MPI/System Bus
IPexpress is especially efficient when generating high pin count modules as it saves time in manually cascading
small library elements from the synthesis library. Detailed information about IPexpress and its user guide can be
found in the ispLEVER help system.