H Series Data Sheet
70 Watt AC-DC Converters
BCD20019 Rev AA
Page 16 of 21
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JFET output (D1 – D4):
Connector pin D is internally connected via the drain-source
path of a JFET (self-conducting type) to the negative potential
of output 1. VD – 0.4 V (logic low) corresponds to a monitored
voltage level (Vi and/or Vo1) < Vt. The current ID through the
JFET should not exceed 2.5 mA. The JFET is protected by a
0.5 W Zener diode of 8.2 V against external overvoltages.
Vi, Vo1 status
D output, VD
Vi or Vo1 < Vt
low, L, VD – 0.4 V at I D = 2.5 mA
Vi and Vo1 > Vt + Vh
high, H, ID – 25 A at VD = 5.25 V
NPN output (D5 – D8):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1. VD – 0.4 V (logic low) corresponds to a monitored
voltage level (Vi and/or Vo1) > Vt + Vh. The current ID through
Vi, Vo1 status
D output, VD
Vi or Vo1 < Vt
high, H, ID – 25 A at VD = 40 V
Vi and Vo1 > Vt + Vh
low, L, VD – 0.4 V at ID = 20 mA
Fig. 18
Options D1 – D4, JFET output
Fig. 19
Options D5 – D8, NPN output
Vo1+
Vo1–
D
VD
ID
Rp
Input
11006
Vo1+
Vo1–
D
VD
ID
Rp
Input
11007a
Threshold tolerances and hysteresis:
If Vi is monitored, the internal input voltage after the input filter
and rectifier is measured. Consequently, this voltage differs
from the voltage at the connector pins by the voltage drop
Vti
across input filter and rectifier. The threshold level of the D1
and D8 options is adjusted in the factory at nominal output
current Io nom and TA = 25 °C.
Fig. 20
Definition of Vti,
Vti, and Vhi (JFET output)
Vti
Vhi
VD low
VD
VD high
Vi
P
o
=
P
onom
P
o
=0
P
o
=0
Vti
P
o
=
P
onom
11021a