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參數(shù)資料
| 型號： | LH1784-2RD8 |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT AC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT PACKAGE-32/11 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 984K |
| 代理商： | LH1784-2RD8 |
H Series Data Sheet
70 Watt AC-DC Converters
BCD20019 Rev AA
Page 9 of 21
www.power-one.com
1.6
0.8
0
–0.8
–50
V
inh [V]
I
inh [mA]
–30
0
–10
10
30
50
2.0
1.2
0.4
–0.4
V
inh = 0.8 V
V
o = on
V
o = off
V
inh = 2.4 V
06032a
Vo–
i
Vo+
I
inh
V
inh
06115a
N
L
Table 5: Output response time tr and tf (see fig. 4). Values not applicable for models equipped with option E.
Type of converter
tr at Po = 0 and tf at Po = Po nom
tr and tf at Po = 3/4 Po nom
tr at Po = Po nom
Unit
typ
max
typ
max
typ
max
LH1001-2R
3
17
3
17
5
25
ms
LH1301-2R
5
25
8
30
10
40
LH1501-2R
3
17
5
25
15
50
LH1601-2R
8
30
15
45
20
70
LH1901-2R
35
100
50
150
85
230
LH2320-9
10
40
15
50
25
80
LH2540-9
8
30
20
40
20
60
LH3020-9
30
85
45
130
75
210
LH3040-9
20
70
30
90
50
150
Auxiliary Functions
i Inhibit
The outputs of the converters may be enabled or disabled by
means of a logic signal (TTL, CMOS, etc.) applied between the
inhibit input i and the negative pin of output 1 (Vo1–). In
systems with several converters, this feature can be used, for
example, to control the activation sequence of the converters.
If the inhibit function is not required, connect the inhibit pin 2 to
pin 23 to enable the outputs (active low logic, fail safe). The
response times are specified in fig. 12.
Fig. 11
Definition of Vinh and Iinh.
Fig. 10
Typical inhibit current Iinh versus inhibit voltage Vinh
Table 4: Inhibit data
Characteristics
Conditions
min
typ
max
Unit
Vinh
Inhibit input voltage to keep
Vo = on
Vi min – Vi max
–50
0.8
V
output voltage
Vo = off
TC min – TC max
2.4
50
I inh
Inhibit current
Vinh = 0
–60
–100
–220
A
0
tr
tf
t
0
Inhibit
1
Vo/Vo nom
0.1
t
0
1
0.95
th
Vi
05025a
Fig. 12
Output response as a function of Vi or inhibit control
Conditions:
R input not connected. For multiple-output models the figures indicated in the table relate to the output, which reacts slowest. All
outputs are resistively loaded. Variation of the input voltage within Vi min – Vi max does not influence the values considerably.
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