參數(shù)資料
型號: LH51BV1000J
廠商: Sharp Corporation
英文描述: CMOS 1M (128K x8) Static Ram(CMOS 1M (128K x8) 靜態(tài)Ram)
中文描述: 100萬的CMOS(128K的× 8)靜態(tài)隨機存儲器(100萬的CMOS(128K的× 8)靜態(tài)羊)
文件頁數(shù): 4/11頁
文件大?。?/td> 77K
代理商: LH51BV1000J
READ CYCLE (T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
CE
1
access time
CE
2
access time
Output enable to output valid
Output hold from address change
CE
1
Low to output active
CE
2
High to output active
OE Low to output active
CE
1
High to output in High impedance
CE
2
Low to output in High impedance
OE High to output in High impedance
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
70
10
5
5
0
70
70
70
40
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
NOTE:
1.
Active output to High impedance to output active tests specified for a
±
200 mV transition from steady state levels into the test load.
WRITE CYCLE (T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Write pulse width
Write recovery time
Input data setup time
Input data hold time
WE High to output active
WE Low to output in High impedance
OE High to output in High impedance
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
t
OHZ
70
60
60
0
55
0
30
0
5
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
NOTE:
1.
Active output to High impedance to output active tests specified for a
±
200 mV transition from steady state levels into the test load.
LH51BV1000J
CMOS 1M (128K
×
8) Static RAM
4
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