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參數(shù)資料
| 型號： | LH5268A |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 64K (8K x 8) Static RAM |
| 中文描述： | 的CMOS 64K的（8K的× 8）靜態(tài)RAM |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 91K |
| 代理商： | LH5268A |
CAPACITANCE
1
(T
A
= 25
°
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
Input/output capacitance
C
IN
C
I/O
V
IN
= 0 V
V
I/O
= 0 V
7
pF
pF
10
NOTE:
1.
This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (T
A
= 0 to +70
°
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Data retention
voltage
V
CCDR
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
- 0.2 V
V
CCDR
= 3 V,
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
- 0.2 V
2.0
5.5
V
1
Data retention
current
I
CCDR
T
A
=
25
°
C
1
μ
A
1
20
μ
A
Chip disable to
data retention
Recovery time
t
CDR
0
ns
t
R
t
RC
ns
2
NOTES:
1.
CE
2
should be
≥
V
CCDR
- 0.2 V or
≤
0.2 V when CE
1
≥
V
CCDR
- 0.2 V
2.
t
RC
= Read cycle time
4.5 V
DATA RETENTION MODE
V
CC
0 V
2.2 V
V
CCDR
CE
1
t
CDR
5268A-6
t
R
CE
1
≥
V
CCDR
- 0.2 V
0 V
V
CCDR
0.8 V
4.5 V
DATA RETENTION MODE
t
CDR
t
R
CE
2
CONTROL
CE
1
CONTROL
(NOTE)
CE
2
0.2 V
≥
NOTE:
To control the data retention mode at CE
1
, fix the input level of CE
2
between V
CCDR
and V
CCDR
- 0.2 V or 0 V to 0.2 V
during the data retention mode.
V
CC
CE
2
Figure 3. Low Voltage Data Retention
CMOS 64K (8K
×
8) Static RAM
LH5268A
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH5268A-10LL | 制造商:Sharp Microelectronics Corporation 功能描述: |
| LH5268AD-10LL | 制造商:Sharp Microelectronics Corporation 功能描述:8K X 8 STANDARD SRAM, 100 ns, PDIP28 |
| LH5268AN-10LL | 制造商:Sharp Microelectronics 功能描述:SRAM Chip Async Single 5V 64K-Bit 8K x 8 100ns 28-Pin SOP |
| LH5278-26-L | 制造商:Klein Tools Inc 功能描述: |
| LH5278-27-L | 制造商:Klein Tools Inc 功能描述: |
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