LH5496/96H
CMOS 512
×
9 FIFO
FEATURES
Fast Access Times:
15 */20/25/35/50/65/80 ns
Full CMOS Dual Port Memory Array
Fully Asynchronous Read and Write
Expandable-in Width and Depth
Full, Half-Full, and Empty Status Flags
Read Retransmit Capability
TTL Compatible I/O
Packages:
28-Pin, 300-mil PDIP
28-Pin, 600-mil PDIP
32-Pin PLCC
Pin and Functionally Compatible with IDT7201
FUNCTIONAL DESCRIPTION
The LH5496/96H are dual port memories with internal
addressing to implement a First-In, First-Out algorithm.
Through an advanced dual port architecture, they provide
fully asynchronous read/write operation. Empty, Full, and
Half-Full status flags are provided to prevent data over-
flow and underflow. In addition, internal logic provides for
unlimited expansion in both word size and depth.
Read and write operations automatically access se-
quential locations in memory in that data is read out in the
same order that it was written, that is on a First-In,
First-Out basis. Since the address sequence is internally
predefined, no external address information is required
for the operation of this device. A ninth data bit is provided
for parity or control information often needed in commu-
nication applications.
Empty, Full, and Half-Full status flags monitor the
extent to which data has been written into the FIFO, and
prevent improper operations (i.e., Read if the FIFO is
empty, or Write if the FIFO is full). A retransmit feature
resets the Read address pointer to its initial position,
thereby allowing repetitive readout of the same data.
Expansion In and Expansion Out pins implement an
expansion scheme that allows individual FIFOs to be
cascaded to greater depth without incurring additional
latency (bubblethrough) delays.
PIN CONNECTIONS
5496-1D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
V
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
FL/RT
RS
EF
XO/HF
R
Q
2
Q
3
Q
8
D
6
D
7
Q
7
Q
6
Q
5
Q
4
28-PIN PDIP
TOP VIEW
Figure 1. Pin Connections for PDIP Packages
5
6
7
8
9
10
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
11
2
3
4
32 31 30
29
28
27
26
25
24
D
6
D
7
NC
EF
D
3
D
8
W
N
V
C
D
4
D
5
14 15 16
20
19
18
17
FL/RT
RS
23
XO/HF
22
Q
7
Q
6
21
12
13
1
Q
3
Q
8
V
S
N
R
Q
4
Q
5
5496-2D
32-PIN PLCC
TOP VIEW
Figure 2. Pin Connections for PLCC Package
* LH5496 only.
1