參數(shù)資料
型號: LH5P8129
廠商: Sharp Corporation
英文描述: CMOS 1M (128K x 8) CS-Control Pseudo-Static RAM
中文描述: 100萬的CMOS(128K的× 8)政務(wù)司司長,控制偽靜態(tài)存儲(chǔ)器
文件頁數(shù): 1/14頁
文件大小: 119K
代理商: LH5P8129
LH5P8129
FEATURES
131,072
×
8 bit organization
Access times (MAX.): 60/80/100 ns
Cycle times (MIN.): 100/130/160 ns
Single +5 V power supply
Pin compatible with 1M standard SRAM
Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (TTL level): 5.5 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
TTL compatible I/O
Available for auto-refresh and self-refresh
modes
512 refresh cycles/8 ms
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8
×
20 mm
2
TSOP (Type I)
DESCRIPTION
The LH5P8129 is a 1M bit Pseudo-Static RAM
organized as 131,072
×
8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while considering the pinout
compatibility with industry standard SRAMs. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8129 PSRAM has a built-in oscillator, which
makes it easy to refresh memories without external
clocks.
PIN CONNECTIONS
5P8129-1
TOP VIEW
5
6
7
8
11
12
A
0
A
3
A
2
26
25
24
23
22
21
18
A
5
A
4
9
10
A
1
20
19
A
6
A
9
A
11
OE
A
10
CE
13
14
15
28
27
I/O
0
I/O
1
A
13
A
8
16
17
I/O
2
GND
A
7
I/O
4
I/O
3
I/O
5
32-PIN DIP
32-PIN SOP
3
4
A
12
30
29
CS
A
14
R/W
1
2
A
16
32
31
V
CC
A
15
RFSH
I/O
6
I/O
7
Figure 1. Pin Connections for DIP and
SOP Packages
CMOS 1M (128K
×
8)
CS-Control Pseudo-Static RAM
2
3
4
5
6
7
9
10
8
A
9
A
8
11
1
32
31
30
29
26
25
28
27
24
23
OE
A
10
32-PIN TSOP (Type I)
12
15
16
13
14
21
20
22
19
17
18
A
11
A
13
R/W
CS
A
15
V
CC
RFSH
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
I/O
7
I/O
6
CE
I/O
5
I/O
4
I/O
3
GND
5P8129-2
A
16
A
14
A
12
A
7
A
6
A
5
A
4
NOTE:
Reverse bend available on request.
TOP VIEW
Figure 2. Pin Connections for TSOP Package
1
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