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參數(shù)資料
| 型號： | LM1238AAF/NA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | N24D |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 1207K |
| 代理商： | LM1238AAF/NA |
Control Register Definitions (Continued)
Contrast Control Register (I
2C address 0x0813h)
Register Name (address): CONTRCTRL (0x0813h)
7
654321
0
RSV
CO
CG
Bits 6–0 Contrast Gain Control. These seven bits determine the overall gain of all the three channels.
Bit 7
Reserved.
DAC2 Register (I
2C address 0x0814h)
Register Name (address): DAC2CTRL (0x0814h)
7
654321
0
D2–7
D2–6
D2–5
D2–4
D2–3
D2–2
D2–1
D2–0
Bits 7–0 These bits determine the output voltage of DAC2.
DAC3 Register (I
2C address 0x0815h)
Register Name (address): DAC3CTRL (0x0815h)
7
654321
0
D3–7
D3–6
D3–5
D3–4
D3–3
D3–2
D3–1
D3–0
Bits 7–0 These bits determine the output voltage of DAC3.
DAC1 Register (I
2C address 0x0816h)
Register Name (address): DAC1CTRL (0x0816h)
7
654321
0
D1–7
D1–6
D1–5
D1–4
D1–3
D1–2
D1–1
D1–0
Bits 7–0 These bits determine the output voltage of DAC1.
DAC4 Register (I
2C address 0x0817h)
Register Name (address): DAC4CTRL (0x0817h)
7
654321
0
D4–7
D4–6
D4–5
D4–4
D4–3
D4–2
D4–1
D4–0
Bits 7–0 These bits determine the output voltage of DAC4.
DCoffset/OSD Contrast/DAC Configuration Control Register (I
2C address 0x0818h)
Register Name (address): DCF/OSD_CON/DC (0x0818h)
7
654321
0
RSV
DCF1
DCF0
OSD
DC2
DC1
DC0
Bits 2–0 DC Offset Control. These three bits determine the active video DC offset to all three channels.
Bits 4–3 OSD Contrast Control. These two bits determine the contrast level of the OSD information.
Bit 5
DAC1–3 Configuration. When this bit is a 0 (default) the DAC outputs of DAC1–3 are full scale (0.5V–4.5V). When this
bit is 1, the range of DAC1–3 are halved (0.5V–2.5V).
Bit 6
DAC4 Configuration. When this bit is a 0 (default), the DAC4 output is not mixed with the other DAC outputs. When the
bit is one, 50% of the DAC4 output is added to DAC1–3.
Bit 7
Reserved.
LM1238
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