![](http://datasheet.mmic.net.cn/220000/LM12434_datasheet_15482066/LM12434_6.png)
2.0 Electrical Specifications
(Continued)
2.2.1 Converter Static Characteristics
The following specifications apply to the LM12434 and LM12
à
L
ó
438 for V
A
a
e
V
D
a
e
5V
à
3.3V
ó
, AGND
e
DGND
e
0V, V
REF
a
e
4.096V
à
2.5V
ó
, V
REF
b
e
0V, 12-bit
a
sign conversion mode, f
CLK
e
8.0 MHz
à
6 MHz
ó
, R
S
e
25
X
, source impedance for V
REF
a
and V
REF
b
s
25
X
, fully-differential input with fixed 2.048V
à
1.25V
ó
common-mode voltage, and minimum acquisition time unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 6, 7, 8 and 9) (Continued)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
DNL
8-Bit
a
Sign and ‘‘Watchdog’’ Mode
Differential Non-Linearity
g
0.15
g
1/2
LSB (max)
8-Bit
a
Sign and ‘‘Watchdog’’ Mode
Zero Error
After Auto-Zero
g
0.05
g
1/2
LSB (max)
8-Bit
a
Sign and ‘‘Watchdog’’ Positive
and Negative Full-Scale Error
g
0.1
g
1/2
LSB (max)
8-Bit
a
Sign and ‘‘Watchdog’’ Mode
DC Common Mode Error
g
1/8
LSB
Multiplexer Channel-to-Channel
Matching
g
0.05
LSB
V
IN
a
Non-Inverting
Input Range
GND
V
A
a
V (min)
V (max)
V
IN
b
Inverting
Input Range
GND
V
A
a
V (min)
V (max)
V
IN
a
b
V
IN
b
Differential Input Voltage Range
b
V
A
a
V
A
a
V (min)
V (max)
V
IN
a
b
V
IN
b
2
Common Mode Input Voltage Range
GND
V
A
a
V (min)
V (max)
PSS
Power Supply
Sensitivity
(Note 15)
Zero Error
V
A
a
e
V
D
a
e
5V
g
10%,
V
REF
a
e
4.096V, V
REF
b
e
GND
g
0.05
g
0.25
g
0.2
g
1.0
g
1.5
LSB (max)
LSB (max)
LSB
Full-Scale Error
Linearity Error
C
REF
V
REF
a
/V
REF
b
Input Capacitance
85
pF
C
IN
Selected Multiplexer Channel Input
Capacitance
75
pF
2.2.2 Converter Dynamic Characteristics
The following specifications apply only to the LM12434 and LM12438 for V
A
a
e
V
D
a
e
5V, AGND
e
DGND
e
0V, V
REF
a
e
4.096V, V
REF
b
e
0V, 12-bit
a
sign conversion mode, f
CLK
e
8.0 MHz,
throughput rate
e
133.3 kHz, R
S
e
25
X
, source impedance for V
REF
a
and V
REF
b
s
25
X
, fully-differential input with fixed
2.048V
à
1.25V
ó
common-mode voltage, and minimum acquisition time unless otherwise specified.
Boldface limits apply
for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 6, 7, 8 and 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
CLK Duty Cycle
50
%
40
60
% (min)
% (max)
t
C
Conversion Time
13-Bit Resolution,
Sequencer State S5(Figure 10)
44 (t
CLK
)
44 (t
CLK
)
a
50 ns
(max)
9-Bit Resolution,
Sequencer State S5(Figure 10)
21 (t
CLK
)
21 (t
CLK
)
a
50 ns
(max)
t
A
Acquisition Time
(Programmable)
Sequencer State S7(Figure 10)
Minimum for 13-Bits
Maximum for 13-Bits (D
e
15)
t
CLK
e
CLK Period
(max)
(max)
9 (t
CLK
)
39 (t
CLK
)
9 (t
CLK
)
a
50 ns
39 (t
CLK
)
a
50 ns
Minimum for 9-Bits(Figure 10)
Maximum for 9-Bits (D
e
15)
2 (t
CLK
)
2 (t
CLK
)
2 (t
CLK
)
a
50 ns
32 (t
CLK
)
a
50 ns
(max)
(max)
6